Many processors can execute Single Instruction Multiple Data (SIMD) instructions to improve program performance by allowing a single instruction to cause multiple, parallel operations to be performed on separate data elements. The registers these instructions operate on are sized large enough to hold a full vector width of input and output operands. However, not all instructions take advantage of this full processing width. In fact, many instructions write to less than a full width of a given processor register (partial register writes). Such operations can be defined to preserve the unmodified portions of a destination register. However, to realize this operation, typically additional instructions are required. While this approach ensures a consistent view of register data values when instructions of differing operand widths are intermixed within a program, it also constrains instruction scheduling and adds unnecessary data copy and other instructions.